1. Field of the Invention
Embodiments of the present invention generally relate to designing first-in first-out (FIFO) memories, and more specifically, to folding the depth and width of the FIFO memory to identify the dimensions of a corresponding memory element.
2. Description of the Related Art
Integrated circuits designed to process data typically use FIFO memories to store data between processing stages. These FIFO memories may have different widths, depths, and different input and output clock frequencies. Conventionally, generators that produce synthesizable code have been used to produce different variations of FIFO memories. However, different physical characteristics of the FIFO memory may lead to inefficiencies. For example, in response to a request, the generator may produce synthesizable code corresponding to a 128×1 FIFO (i.e., a FIFO that has 128 entries that are 1 bit each). However, if this FIFO is implemented using RAM, the width of a RAM cell may be at least 8 bits wide. Accordingly, a 128 deep FIFO would require 128 rows of RAM that are each 8 bits wide. Because each entry stores only one bit, the other seven bits of the row are unused. This inefficiency may lead to the hardware system consuming additional power and requiring more space than is otherwise necessary.